Magnetoresistive random-access memory (“MRAM”) is a non-volatile memory technology that stores data through magnetic storage elements. These elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. This structure is known as a magnetic tunnel junction (“MTJ”). In general, one of the plates has its magnetization pinned (i.e., a “reference layer”), meaning that this layer has a higher coercivity than the other layer and requires a larger magnetic field or spin-polarized current to change the orientation of its magnetization. The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
MRAM devices store information by changing the orientation of the magnetization of the free layer. In particular, based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a “1” or a “0” can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers. The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a “1” and a “0”. One important feature of MRAM devices is that they are non-volatile memory devices, since they maintain the information even when the power is off. The two plates can be sub-micron in lateral size and the magnetization direction can still be stable with respect to thermal fluctuations.
MRAM devices are considered as the next generation structures for a wide range of memory applications. MRAM products based on spin torque transfer switching are already making its way into large data storage devices. Spin transfer torque magnetic random access memory (“STT-MRAM”) or spin transfer switching, uses spin-aligned (“polarized”) electrons to change the magnetization orientation of the free layer in the magnetic tunnel junction. In general, electrons possess a spin, a quantized number of angular momentum intrinsic to the electron. An electrical current is generally unpolarized, i.e., it consists of 50% spin up and 50% spin down electrons. Passing a current though a magnetic layer polarizes electrons with the spin orientation corresponding to the magnetization direction of the magnetic layer (i.e., polarizer), thus produces a spin-polarized current. If a spin-polarized current is passed to the magnetic region of a free layer in the magnetic tunnel junction device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. Thus, this spin transfer torque can switch the magnetization of the free layer, which, in effect, writes either a “1” or a “0” based on whether the free layer is in the parallel or anti-parallel states relative to the reference layer.
STT-MRAM devices belong to a class of devices relying on bipolar memory elements. Bipolar memory elements use currents to “write” data to a memory element. Depending on the direction of current flow, a logic high (1) or logic low (0) bit may be written to the memory element. Such bipolar memory devices may include MRAM, resistive random-access memory (RRAM), phase-change memory (PCM), among others. For example, RRAM devices may utilize memristors as a memory element. Current flowing in one direction may be used to write a logic (1) to the memristor. Current flowing in the opposite direction may be used to write a logic (0) to the memristor.
A typical MRAM device with a polarizer layer and an MTJ is shown in FIG. 1. FIG. 1 illustrates perpendicular magnetic tunnel junction (“MTJ”) stack 100 for a conventional STT-MRAM device. As shown, stack 100 includes one or more seed layers 110 provided at the bottom of stack 100 to initiate a desired crystalline growth in the above-deposited layers. Furthermore, MTJ 130 is deposited on top of SAF layer 120. MTJ 130 includes reference layer 132, which is a magnetic layer, a non-magnetic tunneling barrier layer (i.e., the insulator) 134, and the free layer 136, which is also a magnetic layer. It should be understood that reference layer 132 is actually part of SAF layer 120, but forms one of the ferromagnetic plates of MTJ 130 when the non-magnetic tunneling barrier layer 134 and free layer 136 are formed on reference layer 132. As shown in FIG. 1, magnetic reference layer 132 has a magnetization direction perpendicular to its plane. As also seen in FIG. 1, free layer 136 also has a magnetization direction perpendicular to its plane, but its direction can vary by 180 degrees.
The first magnetic layer 114 in the SAF layer 120 is disposed over seed layer 110. SAF layer 120 also has a antiferromagnetic coupling layer 116 disposed over the first magnetic layer 114. Furthermore, a nonmagnetic spacer 140 is disposed on top of MTJ 130 and an optional polarizer 150 is disposed on top of the nonmagnetic spacer 140. Polarizer 150 is a magnetic layer that in an embodiment has a magnetic direction in its plane, but is perpendicular to the magnetic direction of the reference layer 132 and free layer 136. Polarizer 150 is provided to polarize a current of electrons (“spin-aligned electrons”) applied to MTJ structure 100. Note that in other embodiments, polarizer 150, if present, can also have a magnetic direction perpendicular to its plane, just as the reference layer 132 and free layer 136. Further, one or more capping layers 160 can be provided on top of polarizer 150 to protect the layers below on MTJ stack 100. Finally, a hard mask 170 is deposited over capping layers 160 and is provided to pattern the underlying layers of the MTJ structure 100, using a reactive ion etch (RIE) process.
The resistance of the magnetic memory device is sensitive to the relative orientation of the magnetization vector of the free magnetic layer and the magnetization vector of the reference layer. The resistance of the magnetic memory device is highest when the magnetization vectors of the free magnetic layer and the reference layer, respectively, are in anti-parallel alignment. The resistance of the magnetic device is lowest when the magnetization vectors of the layers free magnetic layer and the reference layer, respectively, are in parallel alignment. Thus, a resistance measurement or its equivalent can determine the orientation of the magnetization vector of the free magnetic layer.
In an MRAM memory write operation, a verify operation can be used to check if a write operation has completed successfully and that the correct data has been written. Typically, a verify operation is performed in a similar fashion to a read operation. For example, a read could be implemented with a bias condition where the bit line is driven to a high potential, while the source line is driven to a low potential to generate current across the MTJ so that the resistance measurement can be made. A verify operation may also be implemented in other bipolar memory elements including RRAM and PCM among others.
In these devices, data is stored in program latches during both write and verify operations. Data stored in the latches (write buffer) determines the voltage condition on bit lines during write operations. In write operations, bit line and source line bias are dependent on the data stored. For example, if the data to be written is logic zero (0), the bit line can be driven high while the source line is driven low. If the data to be written is logic one (1), the opposite bias condition would need to exist in order to reverse the polarity of current flow across the MTJ. In this case for writing logic one (1), the source line would be driven high while the bit line would be driven low.
During either read or verify operations, the bit line is usually at a high voltage (but at a lower voltage than during a write operation) while the source line is at a low voltage, generally close to zero volts. Normally, a write verify operation can be implemented in a similar manner to a read operation. However, the operation presented above can result in what is known as a disturb condition, which occurs when a verify operation is performed after a write logic one (1) operation. In this case, the memory bit is written with the source being driven to a high voltage while the bit line is driven to a low voltage. Thus, during a verify operation, the data would be read with the opposite polarity of the bit line and source line than would normally be done during a read operation. Prior circuitry used for write, read, and verify operations is shown in FIGS. 2A and 2B.
FIG. 2A shows operation of exemplary bipolar memory device 200, in this case, an MRAM device, during write (0), verify, and read operations. Bipolar memory device 200 includes memory cell 202 coupled to source line 208 and bit line 210. Memory cell 202 comprises MTJ 204 and select transistor 206. Select transistor is further coupled to word line 212. MTJ 204 is coupled to bit line 210 and select transistor 206 is coupled to source line 208. One of ordinary skill in the art will understand that the opposite configuration is also possible. That is MTJ 204 could be coupled to source line 208 and select transistor 206 could be coupled to bit line 210.
During write (0), verify, and read operations, voltage node 214 on source line is driven low while voltage node 216 on bit line is driven high. The opposite bias conditions may also be applied for write (0), verify, and read operations and are dependent simply on naming convention for write (0). The reader will also appreciate that verify and read operations occur with the same bias conditions. Voltage node 214 may be driven to ground or otherwise held close to 0V. Voltage node 216 may be driven to a positive voltage. Voltage node 216 is driven to for example, 1.0 V for verify operations; 1.2 V for read operations; and a higher voltage for write operations. Voltage is applied to word line 212 to activate select transistor 206 to allow current i to flow between bit line and source line.
During write (0) operation, the voltage differential across memory cell 202 causes current i to flow. Current i causes the magnetization of free layer of MTJ 204 to align, or become parallel, with the reference layer of MTJ 204. During verify and read operation, the current i is not sufficient to alter the state of free layer and the bit stored in MTJ 204 may be ascertained.
FIG. 2B shows operation of exemplary bipolar memory device 250, in this example, an MRAM device, during write (1) operation. Bipolar memory device 250 includes memory cell 252 coupled to source line 258 and bit line 260. Memory cell 252 comprises MTJ 254 and select transistor 256. Select transistor is further coupled to word line 262. MTJ 254 is coupled to bit line 260 and select transistor 256 is coupled to source line 258. One or ordinary skill in the art will understand that the opposite configuration is also possible. That is MTJ 254 could be coupled to source line 258 and select transistor 256 could be coupled to bit line 260.
Bipolar memory device 250 of FIG. 2B is identical to bipolar memory device 200 of FIG. 2A except that polarity of voltages on source and bit lines are flipped. Thus, voltage node 264 on source line 258 is driven high and voltage node 266 bit line 260 is driven low. Voltage node 264 may also be at a slightly higher voltage for write (1) operation than corresponding voltage on the bit line during write (0) operation. This is because the voltage drop across select transistor 256 is higher in this configuration. Moreover, voltage on word line 262 is chosen to enable current flow. This opposite bias conditions causes current i to flow in the opposite direction from bipolar memory device 200 of FIG. 2A. This results in write (1) operation.
However, performing a write (1) operation as shown in FIG. 2B and then verify operation as shown in FIG. 2A results in disturb condition. This is because opposite bias voltages are applied to source and bit lines for write (1) and verify operations.
Thus, advantageous write-verify operation is necessary to reduce disturb conditions when verifying data bits in bipolar memory devices.